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ASAHI KASEI
[AKD4563A]
AKD4563A
Evaluation board Rev.A for AK4563A
GENERAL DESCRIPTION AKD4563A is an evaluation board for the 16bit 4ch A/D and 2ch D/A converter, AK4563A. The AKD4563A can evaluate A/D converter D/A converter separately in addition to loopback mode (A/D D/A). The A/D section can be evaluated by interfacing with AKM's DAC evaluation boards directly. The AKD4563A has the interface with AKM's wave generator using ROM data and AKM's ADC evaluation boards. Therefore, it's easy to evaluate the D/A section. The AKD4563A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4563A --Evaluation board for AK4563A (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this.)
FUNCTION * Compatible with 2 types of interface - Direct interface with AKM's A/D & D/A converter evaluation boards - DIT/DIR with optical input/output * BNC connector for an external clock input * 10pin Header for serial control mode
VA GND VT
LIN RIN LOUT ROUT
JP13 JP14 AK4563A
CS8412 (DIR)
Opt In
AK4353 (DIT)
Opt Out
Control Data 10pin Header
Clock Generator
A/D, D/A Data ROM Data 10pin Header
Figure 1. AKD4563A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
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ASAHI KASEI
[AKD4563A]
1. Evaluation Board Manual Input / Output circuits & Set-up jumper pin for Input / Output circuits
(1) Input circuits
J2 LIN C37 10u INTL1 C38 10u INTL0 C39 10u EXTL C41 10u LIN + + + +
JP13
R34 560
INT1 INT0 EXT LIN
LIN
J4 RIN
JP14
R38 560
INT1 INT0 EXT RIN
C42 10u INTR1 C44 10u INTR0 C45 10u EXTR C46 10u RIN + + + +
RIN
Figure 2. LIN/RIN Input circuits
1. Analog signal is input to INTL1 and INTR1 pins via J2 and J4 connectors. JP13 LIN INT1 INT0 EXT LIN JP14 RIN INT1 INT0 EXT RIN
2. Analog signal is input to INTL0 and INTR0 pins via J2 and J4 connectors. JP13 LIN INT1 INT0 EXT LIN JP14 RIN INT1 INT0 EXT RIN
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ASAHI KASEI
[AKD4563A]
3. Analog signal is input to EXTL and EXTR pins via J2 and J4 connectors. JP13 LIN INT1 INT0 EXT LIN JP14 RIN INT1 INT0 EXT RIN
4. Analog signal is input to LIN and RIN pins via J2 and J4 connectors. JP13 LIN INT1 INT0 EXT LIN (2) Output circuits Analog signal is output to LOUT and ROUT pins via J3 and J5 connectors.
R35 220 J3 LOUT
JP14 RIN INT1 INT0 EXT RIN
LOUT C40 22u R36 10k
+
ROUT C43 22u R39 10k
Figure 3. LOUT/ROUT output circuits
* AKM assumes no responsibility for the trouble when using the above circuit examples.
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+
R37 220
J5 ROUT
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ASAHI KASEI
[AKD4563A]
Operation sequence
1) Set up the power supply lines. [VA] (orange) = 2.3 3.0V [VT] (orange) = 1.5 3.0V [D2V] (orange) = 1.5 3.0V [D5V] (red) = 3.6 5.0V [AGND] (black) = 0V [DGND] (black) = 0V : for VA of AK4563A (typ. 2.5V) : for VT of AK4563A (typ. 2.5V) : for 74LVC541 (typ. 2.5V) : for logic (typ. 5.0V) : for analog ground : for logic ground
Each supply line should be distributed from the power supply unit. VT and D2V must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4563A and AK4353 should be reset once bringing SW1, 2 "L" upon power-up.
Evaluation mode
Applicable Evaluation Mode 1) Evaluation of loopback mode (default) 2) Evaluation of D/A using ideal sine wave generated by ROM data 3) Evaluation of D/A using A/D converted data 4) Evaluation of D/A using DIR (Optical Link) 5) Evaluation of A/D using D/A converted data 6) Evaluation of A/D using DIT (Optical Link) 7) All interface signals including master clock are fed externally.
1) Evaluation of loopback mode. Nothing should be connected to PORT3 and PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE). When SDTO0 is connected with SDTI, JP8 (SD0/1) selects SD0 side. When SDTO1 is connected with SDTI, JP8 (SD0/1) selects SD1 side. Table 1. AK4563A audio data I/F format and Setting JP3 AK4563A JP3 (X_BCLK) DIF0 SDTO0/SDTO1 (ADC) SDTI (DAC) 0 16bit MSB justified 16bit LSB justified 32fs 1 16bit LSB justified 16bit LSB justified 64fs 0 16bit MSB justified 16bit MSB justified 32fs or 64fs 1 I2S Compatible I2S Compatible 32fs or 64fs
JP4 LRCK JP5 BCLK JP9 SDTI JP10 DIR JP11 CLK JP12 XTE
DIF1 0 0 1 1
JP3 X_BCLK
32fs
64fs
ADC
DIR
ADC
DIR
ADC
DIR
VD
GND EXT XTL DIR
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ASAHI KASEI
[AKD4563A]
2) Evaluation of D/A using A/D converted data from ideal sine wave generated by ROM data. Digital signals generated by AKD43XX are used. PORT3 is used for the interface with AKD43XX. Master clock is sent from AKD4563A to AKD43XX and BCLK, LRCK, SDTI are sent from AKD43XX to AKD4563A. Nothing should be connected to PORT1, PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE).
JP3 X_BCLK JP4 LRCK JP5 BCLK JP9 SDTI JP10 DIR JP11 CLK JP12 XTE
32fs
64fs
ADC
DIR
ADC
DIR
ADC
DIR
VD
GND EXT XTL JP12 XTE XTL DIR
3) Evaluation of D/A using A/D converted data. It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM's A/D evaluation boards with PORT3. Nothing should be connected to PORT1, PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE).
JP3 X_BCLK JP4 LRCK JP5 BCLK JP9 SDTI JP10 DIR JP11 CLK
32fs
64fs
ADC
DIR
ADC
DIR
ADC
DIR
VD
GND EXT DIR
4) Evaluation of D/A using DIR. (Optical link) PORT4 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to PORT1, PORT3. JP3 X_BCLK JP4 LRCK JP5 BCLK JP9 SDTI JP10 DIR JP11 CLK JP12 XTE
32fs
64fs
ADC
DIR
ADC
DIR
ADC
DIR
VD
GND EXT XTL DIR
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ASAHI KASEI
[AKD4563A]
5) Evaluation of A/D using D/A converted data. It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM's D/A evaluation boards with PORT3. Nothing should be connected to PORT4. When SDTO0 is supplied from PORT1, JP8 (SD0/1) selects SD0 side. When SDTO1 is supplied from PORT1, JP8 (SD0/1) selects SD1 side. JP3 X_BCLK JP4 LRCK JP5 BCLK JP9 SDTI JP10 DIR JP11 CLK JP12 XTE
32fs
64fs
ADC
DIR
ADC
DIR
ADC
DIR
VD
GND EXT XTL JP12 XTE XTL JP12 XTE XTL DIR
6) Evaluation of A/D using DIT. (Optical link) PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the digital-amplifier which equips DIR input. Nothing should be connected PORT3 and PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE). When SDTO0 is supplied from PORT1, JP8 (SD0/1) selects SD0 side. When SDTO1 is supplied from PORT1, JP8 (SD0/1) selects SD1 side. JP3 X_BCLK JP4 LRCK JP5 BCLK JP9 SDTI JP10 DIR JP11 CLK
32fs
64fs
ADC
DIR
ADC
DIR
ADC
DIR
VD
GND EXT EXT DIR
7) All interfacing signals (MCLK, BCLK, LRCK) are fed from the external circuit through PORT3. Under the following set up, all external signals needed for the AK4563A to operate could be fed through PORT3. In case of interfacing external sources to D/A converter, JP7 (SDTO) should be open. And in case of using A/D data to externally, JP9 (SDTI) is set ADC side. When JP9 (SDTI) is open, the A/D data can be output from the PORT3, if JP7 (SDTO) is short. JP3 X_BCLK JP4 LRCK JP5 BCLK JP9 SDTI JP10 DIR JP11 CLK
32fs
64fs
ADC
DIR
ADC
DIR
ADC
DIR
VD
GND DIR
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ASAHI KASEI
[AKD4563A]
DIP Switch set up
[SW3] (MODE): Setting evaluation mode of CS8412(DIR) ON is "1", OFF is "0". Table 2. AK4563Aaudio data I/F format and setting SW3 and JP6 AK4563A SW3 MODE DIF1 DIF0 M0 M1 M2 0 0 16bit LSB justified 1 0 1 0 1 16bit LSB justified 1 0 1 1 0 16bit MSB justified 0 0 0 1 1 I2S Compatible 0 1 0 SW3 and AK4563A format must be same audio data format.
JP6 THR THR INV THR
Other jumper pins set up
1. JP1 (GND) : Analog ground and Digital ground OPEN : Separated. SHORT : Common. (The connector "DGND" can be open.) 2. JP2 (VT) : D2V and VT OPEN : Separated. SHORT : Common. (The connector "VT" can be open.) 3. JP6 (PHASE) : Phase of BCLK using DIR THR : BCLK is coincides with AK4563A. (16bit LSB justified and I2S compatible for DAC.) INV : BCLK is inverted. (16bit MSB justified for DAC.) 4. JP7 (SDTO) : Analog ground and Digital ground *Always open. 5. JP8 (SD0/1) : Select SDTO0 or SDTO1 SD0 : Select SDTO0. SD1 : Select SDTO1.
The function of the toggle SW
Upper-side is "H" and lower-side is "L". [SW1] (PDN): Power down of AK4563A. Keep "H" during normal operation. [SW2] (DIT): Power down of AK4353. Keep "H" during normal operation.
Indication for LED
[LED1] (VERF): Monitor VERF pin of the CS8412. LED turns on when some error has occurred to CS8412.
[LED2] (PREM): Indicate whether the input data of CS8412 is pre-emphasized or not.
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ASAHI KASEI
[AKD4563A]
Serial Control
The AK4563A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (CTRL) with PC by 10 wire flat cable packed with the AKD4563A.
Connect PC
CSN CCLK CDTI
AKD4563A
10 wire flat cable
10pin Connector
10pin Header
Figure 4. Connect of 10 wire flat cable
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ASAHI KASEI
[AKD4563A]
2. Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4563A according to previous term. 2. Connect IBM-AT compatible PC with AKD4563A by 10-line type flat cable (packed with AKD4563A). Take care of the direction of 10pin header. (This control software does not operate on Windows NT, therefore please operate it on Windows95/98.) 3. Insert the floppy-disk labeled "AKD4563A Control Program ver 1.0" into the floppy-disk drive. 4. Access the floppy-disk drive and double-click the icon of "AKD4563A.exe" to set up the control program. 5. Then please evaluate according to the follows.
Explanation of each buttons
(1) About AK4563A 1. [Port Setup] : 2. [Write default] : 3. [Function1] : 4. [Function2] : 5. [Write] : (2) About AK4353 1. [MSB] : 2. [LSB] : 3. [I2S] : MSB justified for DIT mode in AK4353. LSB justified for DIT mode in AK4353. I2S compatible for DIT mode in AK4353. Set up the printer port. Initialize the register of AK4563A. Dialog to write data by keyboard operation. Dialog to evaluate IPGA and OPGA. Dialog to write data by mouse operation.
Note 1. Evaluation mode of AK4353 and AK4563A is same mode. Note 2. The default of AK4353 is MCLK=256fs and I2S compatible mode. Note 3. MCLK of AK4353 is fixed to 256fs.
Explanation of each dialog
1. [Function1 Dialog] : Address Box: Data Box: Dialog to write data by keyboard operation
Input register address in 2 figures of hexadecimal. Input register data in 2 figures of hexadecimal.
If you want to write the input data to AK4563A, click "OK" button. If not, click "Cancel" button.
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ASAHI KASEI
[AKD4563A]
2. [Function2 Dialog] :
Dialog to evaluate IPGA
This dialog corresponds to only addr=07H. Address Box: Input register address in 2 figures of hexadecimal. Start Data Box: Input start data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4563A by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4563A, click "OK" button. If not, click "Cancel" button.
3. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the "Write" button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4563A, click "OK" button. If not, click "Cancel" button.
Operation flow
Keep the following flow surely. 1. Set up the control program according to explanation above. 2. Click "Port Setup" button. 3. Click "Write default" button. 4. Set up evaluation mode of AK4353. 5. Then set up the dialog and input data.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
Attention on the operation
If you set up Function1 or Function2 dialog, input data to all boxes. Attention dialog is indicated if you input data or address that is not specified in the datasheet or you click "OK" button before you input data. In that case set up the dialog and input data once more again. These operations does not need if you click "Cancel" button or check the check box.
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ASAHI KASEI
[AKD4563A]
MEASUREMENT RESULTS
[Measurement condition] * Measurement unit: Audio Precision, System Two * MCLK : 256fs * BCLK : 64fs * fs : 48kHz * Bit : 16bit * Power Supply : VA=VD=VT=2.5V * Interface : DIR/DIT * Temperature : Room [Measurement Results] Parameter ADC Analog Input Characteristics S/(N+D) (-2.0dB Input) Input Pin INTL0 / INTR0 INTL1 / INTR1 EXTL / EXTR LIN / RIN INTL0 / INTR0 INTL1 / INTR1 EXTL / EXTR LIN / RIN INTL0 / INTR0 INTL1 / INTR1 EXTL / EXTR LIN / RIN INTL0 / INTR0 INTL1 / INTR1 EXTL / EXTR LIN / RIN Result (Lch / Rch) 86.0 / 86.0 86.0 / 86.0 86.0 / 86.0 85.6 / 85.6 88.6 / 88.6 88.6 / 88.6 88.6 / 88.6 88.1 / 88.1 88.6 / 88.6 88.6 / 88.6 88.6 / 88.6 88.1 / 88.1 106.8 / 108.4 108.1 / 108.2 109.4 / 106.5 107.4 / 107.5 88.0 / 89.0 92.3 / 92.3 92.9 / 92.9 107.8 / 107.0 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
D-Range
(A-weighted)
S/N
(A-weighted)
Interchannel Isolation
DAC Analog Output Characteristics S/(N+D) D-Range (A-weighted) S/N (A-weighted) Interchannel Isolation
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ASAHI KASEI
[AKD4563A]
[ADC Plot]
AKM
A K 4 5 6 3 A A D C T HD+N vs. Input Level VA=VD=VT=2.5V, fs=48kHz, fin=1kHz
-70
-75
-80 d B F S
-85
-90
-95
-100 -120
-110
-100
-90
-80
-70
-60 dBr
-50
-40
-30
-20
-10
Figure 1. THD+N vs. Input Level
AKM
A K 4 5 6 3 A A D C T HD+N vs. Input Frequency VA=VD=VT=2.5V, fs=48kHz, Input=-2.0dBr
-70
-75
-80 d B F S
-85
-90
-95
-100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 2. THD+N vs. Input Frequency
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ASAHI KASEI
[AKD4563A]
AKM
A K 4 5 6 3 A A D C L inearity VA=VD=VT=2.5V, fs=48kHz, fin=1kHz
+0
-20
-40 d B F S
-60
-80
-100
-120 -120
-110
-100
-90
-80
-70
-60 dBr
-50
-40
-30
-20
-10
+0
Figure 3. Linearity
AKM
A K 4 5 6 3 A A D C F requency Response VA=VD=VT=2.5V, fs=48kHz, Input=-2.0dBr
+0 -0.5 -1 -1.5
d B F S
-2 -2.5 -3 -3.5 -4 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 4. Frequency Response
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ASAHI KASEI
[AKD4563A]
AKM
A K 4 5 6 3 A A D C C rosstalk VA=VD=VT=2.5V, fs=48kHz, Input=-2.0dBr
-90 -95 -100 -105
d B
-110 -115 -120 -125 -130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 5. Crosstalk
AKM
A K 4 5 6 3 A A D C F F T P lot VA=VD=VT=2.5V, fs=48kHz, Input=-2.0dBr, fin=1kHz
+0 -20 -40 -60
d B F S
-80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 6. FFT Plot
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ASAHI KASEI
[AKD4563A]
AKM
A K 4 5 6 3 A A D C F F T P lot VA=VD=VT=2.5V, fs=48kHz, Input=-60dBr, fin=1kHz
+0 -20 -40 -60
d B F S
-80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 7. FFT Plot
AKM
A K 4 5 6 3 A A D C F F T P lot VA=VD=VT=2.5V, fs=48kHz, fin=None
+0 -20 -40 -60
d B F S
-80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 8. FFT Plot
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ASAHI KASEI
[AKD4563A]
[DAC Plot]
AKM
A K 4 5 6 3 A D A C T HD+N vs. Input Level VA=VD=VT=2.5V, fs=48kHz, fin=1kHz
-70
-75
-80 d B r A -90
-85
-95
-100 -120
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 1. THD+N vs. Input Level
AKM
A K 4 5 6 3 A D A C T HD+N vs. Input Frequency VA=VD=VT=2.5V, fs=48kHz, Input=0dBFS
-70
-75
-80 d B r A -90
-85
-95
-100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 2. THD+N vs. Input Frequency
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ASAHI KASEI
[AKD4563A]
AKM
A K 4 5 6 3 A D A C L inearity VA=VD=VT=2.5V, fs=48kHz, fin=1kHz
+0 -10 -20 -30
d B r A
-40 -50 -60 -70 -80 -90 -100 -100
-90
-80
-70
-60
-50 dBFS
-40
-30
-20
-10
+0
Figure 3. Linearity
AKM
A K 4 5 6 3 A D A C F requency Response VA=VD=VT=2.5V, fs=48kHz, Input=0dBFS
+1 +0.8 +0.6 +0.4
d B r A
+0.2 +0 -0.2 -0.4 -0.6 -0.8 -1 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
Figure 4. Frequency Response
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ASAHI KASEI
[AKD4563A]
AKM
A K 4 5 6 3 A D A C C rosstalk VA=VD=VT=2.5V, fs=48kHz, Input=0dBFS
-80 -85 -90 -95 -100
d B
-105 -110 -115 -120 -125 -130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 5. Crosstalk
AKM
A K 4 5 6 3 A D A C F F T P lot VA=VD=VT=2.5V, fs=48kHz, Input=0dBFS, fin=1kHz
+0 -20 -40
d B r A
-60 -80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 6. FFT Plot
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ASAHI KASEI
[AKD4563A]
AKM
AK4563A DAC FFT Plot VA=VD=VT=2.5V, fs=48kHz, Input=-60dBFS, fin=1kHz
+0 -20 -40
d B r A
-60 -80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 7. FFT Plot
AKM
AK4563A DAC FFT Plot VA=VD=VT=2.5V, fs=48kHz, fin=None
+0 -20 -40
d B r A
-60 -80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 8. FFT Plot
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A
B
C
D
E
DGND
JP1 GND
AGND
E
E
U1
LOUT
1
LOUT
PDN
28
U2 R1 51
11 Y8 A8 9
ROUT
2
ROUT
CCLK
27
PDN
R2 INTL1
3 INTL1 CSN 26
51
12 Y7 A7 8
CCLK
R3 INTR1
D
51
13 Y6 A6 7
4
INTR1
CDTI
25
CSN
D
R4 INTL0
5 INTL0 CDTO 24
51
14 Y5 A5 6
CDTI
R5 INTR0
6 INTR0 BCLK 23
51
CDTO
15 Y4 A4 5
BCLK
R6 EXTL
7 EXTL MCLK 22
51
16 Y3 A3 4
MCLK
R7 EXTR
8 EXTR LRCK 21
51
17 Y2 A2 3
LRCK
R8 LIN
9 LIN SDTI 20
51
18 Y1 A1 2
SDTI
11
VCOM
SDTO0
18
SDTO0 D2V
C3 2.2u C6 10u
+ C4 0.1u
12 AGND VT 17
C7 0.1u
13 VA DGND 16
C8 0.1u C9 0.1u
14 VREF VD 15
+ C5 10u + C10 10u
VA L2
B
AK4563A
1 2
C11 47u
+
(short)
R9 10
1
2
L3 10u
2
VT
JP2 VT 2VD +
C12 47u
1
3
1
A
2
A
B
C
+
1
C
RIN
10
RIN
SDTO1
19
SDTO1
C1 47u
2
C2 0.1u
10
GND
G2
19
C
20
VCC
G1
1
L1 10u 74LVC541
+
2VD
VD
B
D1 1S1588
R10 10k
1
U3A
2
3
U3B
4
PDN
L
H SW1 PDN C13 0.1u
74HC14
74HC14
A
Title Size Document Number
AKD4563A
AK4563A
Sheet
E
Rev
A3
Date:
D
A 1
of
Friday, October 20, 2000
3
A
B
C
D
E
VD PORT1
5 6 5 6 IN VCC IF GND 4 3 2 1
VD
E
VD
DIT
R11 1k
C14 0.1u
E
R12 10k
2
R13 10k
R14 10k
R15 1k
D2 1S1588
1
R16 10k
5
U3C 74HC14
6 9
U3D 74HC14
8
R17 470 C16 0.1u C15 10u + U4
1 2 3 4 5 6 7 8 9 10 11 12 MCKO TX DVDD DVSS MCKI BICK SDTI LRCK PDN CSN SCL/CCLK SDA/CDTI DZF NC AVDD AVSS VCOM AOUTL AOUTR CAD0 CAD1 I2C TTL TST 24 23 22 21 20 19 18 17 16 15 14 13
R18 5.1
CSN VD R19 470 CCLK C18 0.1u C19 + 10u + C21 10u PORT2
10 9 8 7 6 1 2 3 4 5
3
1
L
H SW2 DIT
C17 0.1u
CSN CCLK CDTI CDTO
R20 470 CDTI R21 51
2
2
U5A SN74LVC07A
1
CTRL
CDTO
D
D
SDTO
C20 0.1u
R22 51 R23 51
AK4353 CDTI CCLK U6
10 11 CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
VD 64fs + C22 47u
X_LRCK DIR_LRCK
ADC DIR
JP4 LRCK
R24 51 CSN
JP3 X_BCLK X_BCLK
C23 0.1u
C24 0.1u
C25 0.1u
C
X_BCLK
ADC DIR
JP5 BCLK SDTO
fs
32fs
for 74HCU04, 74HC14, 74HC4040 X_LRCK
C
74HC4040
VD C26 0.1u R25 1k R26 1k
4
2VD
THR JP6 PHASE INV
10
BCLK LRCK U3E 74HC14
11
MCLK BCLK LRCK SDTI ROM
PORT3
1 2 3 4 5 10 9 8 7 6 SDTO
JP7 SDTO ADC
for SN74LVC07A
ROM R27 10k
VD
JP9 SDTI SDTI
SD0 JP8 SD0/1
U5B SN74LVC07A
3
SDTO0
DIR DIR_BCLK JP10 DIR R28 1k VD
1
U5C SN74LVC07A
6 5
VD
SD1
SDTO1
B
B
GND
VD
1
LED1
2
R29 1k
12
U3F 74HC14
13
MCLK X1 JP11 CLK DIR EXT XTL
2 1
VERF
1
L4
2
12.288MHz R30 1M U8A
3 2 1
10u L5 47u
1
LED2 PREM
2
6 5
6 5
GND VCC GND OUT
4 3 2 1
2
PORT4
R31 1k
U7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 C Cd/F1 Cc/F0 Cb/E2 Ca/E1 C0/E0 VD+ DGND RXP RXN FSYNC SCK CS12/FCK U VERF Ce/F2 SDATA ERF M1 M0 VA+ AGND FILT MCK M2 M3 SEL CBL 28 27 26 25 24 23 22 21 20 19 18 17 16 15
+
C27 10u
4
U8B 74HCU04
JP12 XTE
DIR
A
C31 0.1u
+ C32 10u
M0
M1
C28 0.1u
74HCU04 C29 (open)
C30 (open)
C33 0.01u DIR_LRCK DIR_BCLK
C35 0.1u C36 0.01u
M2
R32 1k
C34 47n
6
U8C
5
J1 EXT
Title
A
CS8412
74HCU04
R33 51
Size
Document Number
AKD4563A
Interface
Sheet
E
Rev
A3
Date:
B C D
A 2
of
Friday, October 20, 2000
3
A
A
B
C
D
E
E
E
J2 LIN
JP13
R34 560
D
INT1 INT0 EXT LIN
C37 10u INTL1 C38 10u INTL0 + C39 10u EXTL C41 10u LIN + LOUT C40 22u R36 10k + R35 220 J3 LOUT
D
+
LIN
+
J4 RIN
JP14
C
R38 560
INT1 INT0 EXT RIN
C42 10u INTR1 C44 10u INTR0 C45 10u EXTR C46 10u RIN + + + ROUT C43 22u R39 10k + +
R37 220
J5 ROUT
C
RIN
VD SW3
1 2 3 6 5 4
B
M2 M1 M0
U8D 74HCU04
8 9 8
U5D SN74LVC07A
9 11
U5E SN74LVC07A
10
B
MODE
RP1
3 2 1
U8E 74HCU04 M2 M1 M0
10 11 12
U5F SN74LVC07A
13
47k
12
U8F 74HCU04
13
A
A
Title Size Document Number
AKD4563A
Input/Output
Sheet
E
Rev
A3
Date:
A B C D
A 3
of
Friday, October 20, 2000
3
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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